Electroless deposition of Co is performed in a variety of applications in the manufacture of microelectronic devices. For example, Co is used in capping of damascene Cu metallization employed to form electrical interconnects in integrated circuit substrates. Copper can diffuse rapidly into a Si substrate and dielectric films such as, for example, SiO2 or low k dielectrics. Copper can also diffuse into a device layer built on top of a substrate in multilayer device applications. Such diffusion can be detrimental to the device because it can cause electrical leakage in substrates, or form an unintended electrical connection between two interconnects resulting in an electrical short. Moreover, Cu diffusion out of an interconnect feature can disrupt electrical flow. Copper also has a tendency to migrate from one location to another when electrical current passes through interconnect features in service, creating voids and hillocks. This migration can damage an adjacent interconnect line and disrupt electrical flow in the feature where the metal migrates. Cobalt capping is employed to inhibit this Cu diffusion and migration.
Accordingly, among the challenges facing integrated circuit device manufacturers is to minimize diffusion and electromigration of metal in metal-filled interconnect features. This challenge becomes more acute as the devices further miniaturize, and as the features further miniaturize and densify.
Another challenge in the context of metal interconnect features is to protect them from corrosion. Certain interconnect metals, especially Cu, are more susceptible to corrosion. Copper is a fairly reactive metal which readily oxidizes under ambient conditions. This reactivity can undermine adhesion to dielectrics and thin films, resulting in voids and delamination. Another challenge is therefore to combat oxidation and enhance adhesion between the cap and the Cu, and between structure layers.
The industry has deposited Co-based caps over Cu and other metal interconnect features, as discussed in, for example, U.S. Pat. Pub. No. 2003/0207560 and U.S. patent application Ser. No. 10/867,346.
A particular Co-based metal capping layer employed to reduce Cu migration, provide corrosion protection, and enhance adhesion between the dielectric and Cu is a ternary alloy including Co, W, and P. Another refractory metal may replace or be used in addition to W, and B is often substituted for or used in addition to P. Each component of the ternary alloy imparts advantages to the protective layer.
A particular problem for the integration of this technology to current ULSI fabrication lines is high defectivity of the capping layer. In recent years, the defectivity has been an object in inventions relating to plating baths and tools. See Katakabe et al. (U.S. Pat. Pub. No. 2004/0245214), Kolics et al. (U.S. Pat. Pub. No. 2004/0134375), Dubin et al. (U.S. Pat. Pub. No. 2005/0008786), Cheng et al. (U.S. Pat. Pub. No. 2004/0253814), Weidman et al. (U.S. Pat. Pub. No. 2005/0084615), Pancham et al. (U.S. Pat. Pub. No. 2005/0072525), and Saijo et al. (U.S. Pat. Pub. No. 2005/0009340). Defectivity reduction remains a challenge in ULSI fabrication lines.
Typical defects in electroless plated cobalt alloys for use as caps on interconnect features may be summarized as follows.
Nodulation: localized preferential growth or particle formation on the Cu deposit, at Cu/dielectric and Cu/barrier interfaces, and on dielectric surfaces. This problem may be generally caused by a lack of stability of the working bath, and formation of incubation centers in the solution, such as Co3+ due to the oxidation of Co2+ by dissolved oxygen.
“Grain decoration”: uneven morphology of electroless Co film along the Cu line that replicates Cu erosion before plating and/or unevenly grown Co film due to initiation delay at Cu grain interfaces. Such growth can contribute to overall deposit roughness.
Granularity: irregularly sized nanocrystallites and clusters of amorphous electroless deposits of Co and its alloys with large grains and well-defined grain interfaces. This type of morphology can contribute to surface roughness.
Non-uniform growth: varying deposit thickness along the Cu substrate due to different plating rate of electroless Co on different size features, features located in different areas, dense and isolated, and/or features with different surface areas.
Pitting: the formation of pits or pinholes due to localized incomplete Cu surface coverage or extensive hydrogen bubble formation during the deposition process of the electroless film.
Those defects decrease diffusion barrier effectiveness, lower the capability of the capping layer to suppress electromigration, cause electromigration failure, affect the signal propagation across the circuitry, increase current leakage, and may even result in electrical shorts.
Therefore, a need continues to exist for substantially defect free, uniform, and smooth electrolessly deposited capping layers over Cu interconnects.